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ltc2637 1 2637fb octal 12-/10-/8-bit i 2 c v out dacs with 10ppm/c reference features applications description the ltc ? 2637 is a family of octal 12-, 10-, and 8-bit voltage-output dacs with an integrated, high-accuracy, low-drift 10ppm/c reference in 14-lead dfn and 16-lead msop packages. it has a rail-to-rail output buffer and is guaranteed monotonic. the ltc2637-l has a full-scale output of 2.5v, and operates from a single 2.7v to 5.5v supply. the ltc2637-h has a full-scale output of 4.096v, and operates from a 4.5v to 5.5v supply. each dac can also operate with an external reference, which sets the dac full-scale output to the external reference voltage. these dacs communicate via a 2-wire i 2 c-compatible serial interface. the ltc2637 operates in both the standard mode (clock rate of 100khz) and the fast mode (clock rate of 400khz). the ltc2637 incorporates a power-on reset circuit. options are available for reset to zero-scale or reset to mid-scale in internal reference mode, or reset to mid-scale in external reference mode after power-up. n integrated precision reference: 2.5v full-scale 10ppm/c (ltc2637-l) 4.096v full-scale 10ppm/c (ltc2637-h) n maximum inl error: 2.5lsb (ltc2637-12) n low noise: 0.75mv p-p 0.1hz to 200khz n guaranteed monotonic over C40c to 125c temperature range n selectable internal or external reference n 2.7v to 5.5v supply range (ltc2637-l) n ultralow crosstalk between dacs (<3nv?s) n low power: 100a per dac at 3v (ltc2637-l) n power-on-reset to zero-scale/mid-scale n double-buffered data latches n tiny 14-lead 4mm 3mm dfn and 16-lead msop packages n mobile communications n process control and industrial automation n automatic test equipment n portable equipment n automotive n optical networking block diagram integral nonlinearity (ltc2637-lz12) 2637 bd gnd v outa v outb v outc v outd cao (ca1) (ca2) ref v cc v outh v outg v outf v oute scl internal reference switch dac a decode power-on reset v ref v ref v ref v ref v ref v ref v ref dac b dac c dac d dac h dac g dac f dac e register i 2 c address decode ( ) msop package only register register register register register register register register register register register register register register register sda i 2 c interface code 0 inl (lsb) 2 1 0 C1 C2 1024 3072 2637 ta01 4095 2048 v cc = 3v internal ref. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5396245, 5859606, 6891433, 6937178, 7414561.
ltc2637 2 2637fb absolute maximum ratings 1 2 3 4 5 6 7 14 13 12 11 10 9 8 gnd v outh v outg v outf v oute ref sda v cc v outa v outb v outc v outd ca0 scl top view de package 14-lead (4mm s 3mm) plastic dfn 15 t jmax = 150c, ja = 37c/w exposed pad (pin 15) is gnd, must be soldered to pcb 1 2 3 4 5 6 7 8 v cc v outa v outb v outc v outd ca2 ca0 scl 16 15 14 13 12 11 10 9 gnd v outh v outg v outf v oute ref ca1 sda top view ms package 16-lead (4mm s 5mm) plastic msop t jmax = 150c, ja = 110c/w pin configuration supply voltage (v cc ) ................................... C0.3v to 6v scl, sda ..................................................... C0.3v to 6v v outa - v outh , ca0, ca1, ca2 ...................C0.3v to min(v cc + 0.3v, 6v) ref ...................................C0.3v to min(v cc + 0.3v, 6v) operating temperature range ltc2637c ................................................ 0c to 70c (notes 1, 2) ltc2637i ............................................. C40c to 85c ltc2637h (note 3) ............................ C40c to 125c maximum junction temperature .......................... 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) ms package ...................................................... 300c
ltc2637 3 2637fb order information ltc2637 c de Cl z 12 #tr pbf lead free designator tape and reel tr = 2500-piece tape and reel resolution 12 = 12-bit 10 = 10-bit 8 = 8-bit power-on reset mi = reset to mid-scale in internal reference mode mx = reset to mid-scale in external reference mode z = reset to zero-scale in internal reference mode full-scale voltage, internal reference mode l = 2.5v h = 4.096v package type de = 14-lead dfn ms = 16-lead msop temperature grade c = commercial temperature range (0c to 70c) i = industrial temperature range (C40c to 85c) h = automotive temperature range (C40c to 125c) product part number consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc2637 4 2637fb part number part marking * v fs with internal reference power-on reset to code power-on reference mode resolution v cc maximum inl dfn msop ltc2637-lmi12 ltc2637-lmi10 ltc2637-lmi8 7lmi2 7lmi1 7lmi8 7lmi12 7lmi10 37lmi8 2.5v ? (4095/4096) 2.5v ? (1023/1024) 2.5v ? (255/256) mid-scale mid-scale mid-scale internal internal internal 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2637-lmx12 LTC2637-LMX10 ltc2637-lmx8 7lmx2 7lmx1 7lmx8 7lmx12 7lmx10 37lmx8 2.5v ? (4095/4096) 2.5v ? (1023/1024) 2.5v ? (255/256) mid-scale mid-scale mid-scale external external external 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2637-lz12 ltc2637-lz10 ltc2637-lz8 7lz12 7lz10 37lz8 37lz12 37lz10 637lz8 2.5v ? (4095/4096) 2.5v ? (1023/1024) 2.5v ? (255/256) zero-scale zero-scale zero-scale internal internal internal 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2637-hmi12 ltc2637-hmi10 ltc2637-hmi8 7hmi2 7hmi1 7hmi8 7hmi12 7hmi10 37hmi8 4.096v ? (4095/4096) 4.096v ? (1023/1024) 4.096v ? (255/256) mid-scale mid-scale mid-scale internal internal internal 12-bit 10-bit 8-bit 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2637-hmx12 ltc2637-hmx10 ltc2637-hmx8 7hmx2 7hmx1 7hmx8 7hmx12 7hmx10 37hmx8 4.096v ? (4095/4096) 4.096v ? (1023/1024) 4.096v ? (255/256) mid-scale mid-scale mid-scale external external external 12-bit 10-bit 8-bit 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2637-hz12 ltc2637-hz10 ltc2637-hz8 7hz12 7hz10 37hz8 37hz12 37hz10 637hz8 4.096v ? (4095/4096) 4.096v ? (1023/1024) 4.096v ? (255/256) zero-scale zero-scale zero-scale internal internal internal 12-bit 10-bit 8-bit 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 2.5lsb 1lsb 0.5lsb *above options are available in a 14-lead dfn package (ltc2637xde) or 16-lead msop package (ltc2637xms). product selection guide
ltc2637 5 2637fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. symbol parameter conditions min typ max units v out dac output span external reference internal reference 0 to v ref 0 to 2.5 v v psr power supply rejection v cc = 3v10% or 5v10% C80 db i sc short circuit output current (note 6) sinking sourcing v fs = v cc = 5.5v zero-scale; v out shorted to v cc full-scale; v out shorted to gnd l l 27 C28 48 C48 ma ma power supply v cc positive supply voltage for speci? ed performance l 2.7 5.5 v i cc supply current (note 7) v cc = 3v, v ref =2.5v, external reference v cc = 3v, internal reference v cc = 5v, v ref =2.5v, external reference v cc = 5v, internal reference l l l l 0.8 0.9 0.9 1 1.1 1.3 1.3 1.5 ma ma ma ma i sd supply current in power-down mode (note 7) v cc = 5v, c-grade, i-grade v cc = 5v, h-grade l l 1 1 20 30 a a ltc2637-lmi12/ ltc2637-lmi10/ ltc2637-lmi8/ ltc2637-lmx12/ LTC2637-LMX10/ ltc2637-lmx8/ ltc2637-lz12/ ltc2637-lz10/ ltc2637-lz8 (v fs = 2.5v) symbol parameter conditions ltc2637-8 ltc2637-10 ltc2637-12 units min typ max min typ max min typ max resolution l 8 10 12 bits monotonicity v cc = 3v, internal reference (note 4) l 8 10 12 bits dnl differential nonlinearity v cc = 3v, internal reference (note 4) l 0.5 0.5 1 lsb inl integral nonlinearity v cc = 3v, internal reference (note 4) l 0.05 0.5 0.2 1 1 2.5 lsb zse zero-scale error v cc = 3v, internal reference, code = 0 l 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 3v, internal reference (note 5) l 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coef? cient v cc =3v, internal reference 10 10 10 v/c ge gain error v cc = 3v, internal reference l 0.2 0.8 0.2 0.8 0.2 0.8 %fsr ge tc gain temperature coef? cient v cc = 3v, internal reference (note 10) c-grade i-grade h-grade 10 10 10 10 10 10 10 10 10 ppm/c ppm/c ppm/c load regulation internal reference, mid-scale, v cc = 3v10%, C5ma i out 5ma v cc = 5v10%, (note 15) C10ma i out 10ma l l 0.009 0.009 0.016 0.016 0.035 0.035 0.064 0.064 0.14 0.14 0.256 0.256 lsb/ma lsb/ma r out dc output impedance internal reference, mid-scale, v cc = 3v10%, C5ma i out 5ma v cc = 5v10%, (note 15) C10ma i out 10ma l l 0.09 0.09 0.156 0.156 0.09 0.09 0.156 0.156 0.09 0.09 0.156 0.156
ltc2637 6 2637fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2637-lmi12/ ltc2637-lmi10/ ltc2637-lmi8/ ltc2637-lmx12/ LTC2637-LMX10/ ltc2637-lmx8/ ltc2637-lz12/ ltc2637-lz10/ ltc2637-lz8 (v fs = 2.5v) symbol parameter conditions min typ max units reference input input voltage range l 1v cc v resistance l 120 160 200 k capacitance 12 pf i ref reference current, power-down mode dac powered down l 0.005 1.5 a reference output output voltage l 1.24 1.25 1.26 v reference temperature coef? cient 10 ppm/c output impedance 0.5 k capacitive load driving 10 f short circuit current v cc = 5.5v; ref shorted to gnd 2.5 ma digital i/o v il low level input voltage (sda and scl) (note 14) l C0.5 0.3v cc v v ih high level input voltage (sda and scl) (note 11) l 0.7v cc v v il(ca n ) low level input voltage on ca n (n = 0, 1, 2) see test circuit 1 l 0.15v cc v v ih(ca n ) high level input voltage on ca n (n = 0, 1, 2) see test circuit 1 l 0.85v cc v r inh resistance from ca n (n=0, 1,2) to v cc to set ca n = v cc see test circuit 2 l 10 k r inl resistance from ca n (n=0, 1,2) to gnd to set ca n = gnd see test circuit 2 l 10 k r inf resistance from ca n (n=0, 1,2) to v cc or gnd to set ca n = float see test circuit 2 l 2m v ol low level output voltage sink current = 3ma l 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 12) l 20 + 0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 050ns i in input leakage 0.1v cc v in 0.9v cc l 1 a c in i/o pin capacitance (note 8) l 10 pf c b capacitive load for each bus line l 400 pf c ca n external capacitive load on address pin ca n (n=0, 1,2) l 10 pf
ltc2637 7 2637fb ltc2637-lmi12/ ltc2637-lmi10/ ltc2637-lmi8/ ltc2637-lmx12/ LTC2637-LMX10/ ltc2637-lmx8/ ltc2637-lz12/ ltc2637-lz10/ ltc2637-lz8 (v fs = 2.5v) symbol parameter conditions min typ max units ac performance t s settling time v cc = 3v (note 9) 0.39% (1lsb at 8 bits) 0.098% (1lsb at 10 bits) 0.024% (1lsb at 12 bits) 3.5 4.1 4.5 s s s voltage output slew rate 1.0 v/s capacitive load driving 500 pf glitch impulse at mid-scale transition 2.1 nv?s dac-to-dac crosstalk 1 dac held at fs, 1 dac switched 0 to fs 2.6 nv?s multiplying bandwidth external reference 320 khz e n output voltage noise density at f = 1khz, external reference at f = 10khz, external reference at f = 1khz, internal reference at f = 10khz, internal reference 180 160 200 180 nv/ hz nv/ hz nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, external reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, external reference 0.1hz to 200khz, internal reference 35 40 680 730 v p-p v p-p v p-p v p-p electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2637-lmi12/ ltc2637-lmi10/ ltc2637-lmi8/ ltc2637-lmx12/ LTC2637-LMX10/ ltc2637-lmx8/ ltc2637-lz12/ ltc2637-lz10/ ltc2637-lz8 (v fs = 2.5v) symbol parameter conditions min typ max units f scl scl clock frequency l 0 400 khz t hd(sta) hold time (repeated) start condition l 0.6 s t low low period of the scl clock pin l 1.3 s t high high period of the scl clock pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t f fall time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v. (see figure 1) (note 13)
ltc2637 8 2637fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2637-hmi12/ ltc2637-hmi10/ ltc2637-hmi8/ ltc2637-hmx12/ ltc2637-hmx10/ ltc2637-hmx8/ ltc2637-hz12/ ltc2637-hz10/ ltc2637-hz8 (v fs =4.096v) symbol parameter conditions ltc2637-8 ltc2637-10 ltc2637-12 units min typ max min typ max min typ max resolution l 8 10 12 bits monotonicity v cc = 5v, internal reference (note 4) l 8 10 12 bits dnl differential nonlinearity v cc = 5v, internal reference (note 4) l 0.5 0.5 1 lsb inl integral nonlinearity v cc = 5v, internal reference (note 4) l 0.05 0.5 0.2 1 1 2.5 lsb zse zero-scale error v cc = 5v, internal reference, code = 0 l 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 5v, internal reference (note 5) l 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coef? cient v cc = 5v, internal reference 10 10 10 v/c ge gain error v cc = 5v, internal reference l 0.2 0.8 0.2 0.8 0.2 0.8 %fsr ge tc gain temperature coef? cient v cc = 5v, internal reference (note 10) c-grade i-grade h-grade 10 10 10 10 10 10 10 10 10 ppm/c ppm/c ppm/c load regulation v cc = 5v10%, (note 15) internal reference, mid-scale, C10ma i out 10ma l 0.006 0.01 0.022 0.04 0.09 0.16 lsb/ma r out dc output impedance v cc = 5v10%, (note 15) internal reference, mid-scale, C10ma i out 10ma l 0.09 0.156 0.0 9 0.156 0.09 0.156 symbol parameter conditions min typ max units v out dac output span external reference internal reference 0 to v ref 0 to 4.096 v v psr power supply rejection v cc = 5v10% C80 db i sc short circuit output current (note 6) sinking sourcing v fs = v cc = 5.5v zero-scale; v out shorted to v cc full-scale; v out shorted to gnd l l 27 C28 48 C48 ma ma power supply v cc positive supply voltage for speci? ed performance l 4.5 5.5 v i cc supply current (note 7) v cc = 5v, v ref = 4.096v, external reference v cc = 5v, internal reference l l 1.0 1.1 1.3 1.5 ma ma i sd supply current in power-down mode (note 7) v cc = 5v, c-grade, i-grade v cc = 5v, h-grade l l 1 1 20 30 a a reference input input voltage range l 1v cc v resistance l 120 160 200 k capacitance 12 pf i ref reference current, power-down mode dac powered down l 0.005 1.5 a reference output output voltage l 2.032 2.048 2.064 v reference temperature coef? cient 10 ppm/c
ltc2637 9 2637fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2637-hmi12/ ltc2637-hmi10/ ltc2637-hmi8/ ltc2637-hmx12/ ltc2637-hmx10/ ltc2637-hmx8/ ltc2637-hz12/ ltc2637-hz10/ ltc2637-hz8 (v fs =4.096v) symbol parameter conditions min typ max units output impedance 0.5 k capacitive load driving 10 f short circuit current v cc = 5.5v; ref shorted to gnd 4 ma digital i/o v il low level input voltage (sda and scl) (note 14) l C0.5 0.3v cc v v ih high level input voltage (sda and scl) (note 11) l 0.7v cc v v il(ca n ) low level input voltage on ca n (n = 0, 1, 2) see test circuit 1 l 0.15v cc v v ih(ca n ) high level input voltage on ca n (n = 0, 1, 2) see test circuit 1 l 0.85v cc v r inh resistance from ca n (n=0, 1,2) to v cc to set ca n = v cc see test circuit 2 l 10 k r inl resistance from ca n (n=0, 1,2) to gnd to set ca n = gnd see test circuit 2 l 10 k r inf resistance from ca n (n=0, 1,2) to v cc or gnd to set ca n = float see test circuit 2 l 2m v ol low level output voltage sink current = 3ma l 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 12) l 20 + 0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 050ns i in input leakage 0.1v cc v in 0.9v cc l 1 a c in i/o pin capacitance (note 8) l 10 pf c b capacitive load for each bus line l 400 pf c ca n external capacitive load on address pin ca n (n=0, 1,2) l 10 pf ac performance t s settling time v cc = 3v (note 9) 0.39% (1lsb at 8 bits) 0.098% (1lsb at 10 bits) 0.024% (1lsb at 12 bits) 3.9 4.3 5 s s s voltage output slew rate 1 v/s capacitive load driving 500 pf glitch impulse at mid-scale transition 3 nv?s dac-to-dac crosstalk 1 dac held at fs, 1 dac switched 0 to fs 3 nv?s multiplying bandwidth external reference 320 khz e n output voltage noise density at f = 1khz, external reference at f = 10khz, external reference at f = 1khz, internal reference at f = 10khz, internal reference 180 160 250 230 nv/ hz nv/ hz nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, external reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, external reference 0.1hz to 200khz, internal reference 35 50 680 750 v p-p v p-p v p-p v p-p
ltc2637 10 2637fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are with respect to gnd. note 3: high temperatures degrade operating lifetimes. operating lifetime is derated at temperatures greater than 105c. operating at temperatures above 110c and with v cc > 4v requires v cc slew rates to be no greater than 110mv/ms. note 4: linearity and monotonicity are de? ned from code k l to code 2 n C1, where n is the resolution and k l is given by k l = 0.016?(2 n / v fs ), rounded to the nearest whole code. for v fs = 2.5v and n = 12, k l = 26 and linearity is de? ned from code 26 to code 4,095. for v fs = 4.096v and n = 12, k l = 16 and linearity is de? ned from code 16 to code 4,095. note 5: inferred from measurement at code 16 (ltc2637-12), code 4 (ltc2637-10) or code 1 (ltc2637-8), and at full-scale. note 6: this ic includes current limiting that is intended to protect the device during momentary overload conditions. junction temperature can exceed the rated maximum during current limiting. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 7: digital inputs at 0v or v cc . note 8: guaranteed by design and not production tested. note 9: internal reference mode. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k in parallel with 100pf to gnd. note 10: temperature coef? cient is calculated by dividing the maximum change in output voltage by the speci? ed temperature range. note 11: maximum v ih = v cc(max) + 0.5v. note 12: c b = capacitance of one bus line in pf. note 13: all values refer to v ih = v in(min) and v il = v il(max) levels. note 14: minimum v il exceeds absolute maximum rating. this condition wont damage the ic, but could degrade performance. note 15: thermal resistance of msop package limits i out to C5ma i out 5ma for h-grade msop parts and v cc = 5v 10%. ltc2637-hmi12/ ltc2637-hmi10/ ltc2637-hmi8/ ltc2637-hmx12/ ltc2637-hmx10/ ltc2637-hmx8/ ltc2637-hz12/ ltc2637-hz10/ ltc2637-hz8 (v fs =4.096v) symbol parameter conditions min typ max units f scl scl clock frequency l 0 400 khz t hd(sta) hold time (repeated) start condition l 0.6 s t low low period of the scl clock pin l 1.3 s t high high period of the scl clock pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t f fall time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s timing characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc =4.5v to 5.5v. (see figure 1) (note 13).
ltc2637 11 2637fb typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature dnl vs temperature reference output voltage vs temperature settling to 1lsb rising settling to 1lsb falling t a = 25c, unless otherwise noted. ltc2637-l12 (internal reference, v fs = 2.5v) code 0 inl (lsb) 1.0 0.5 0 C0.5 C1.0 1024 3072 2637 g01 4095 2048 v cc = 3v code 0 dnl (lsb) 1.0 0.5 0 C0.5 C1.0 1024 3072 2637 g02 4095 2048 v cc = 3v temperature (c) C50 inl (lsb) 1.0 0.5 0 C0.5 C1.0 C25 125 100 75 50 25 2637 g03 150 0 v cc = 3v inl (pos) inl (neg) temperature (c) C50 dnl (lsb) 1.0 0.5 0 C0.5 C1.0 C25 125 100 75 50 25 2637 g04 150 0 v cc = 3v dnl (pos) dnl (neg) temperature (c) C50 v ref (v) 1.260 1.255 1.250 1.245 1.240 C25 125 100 75 50 25 2637 g05 150 0 v cc = 3v scl 5v/div v out 1lsb/div 2s/div 2637 g06 9th clock of 3rd data byte 1/4 scale to 3/4 scale step v cc = 3v, v fs = 2.5v r l = 2k, c l = 100pf average of 256 events 3.6s scl 5v/div v out 1lsb/div 2s/div 2637 g07 9th clock of 3rd data byte 3/4 scale to 1/4 scale step v cc = 3v, v fs = 2.5v r l = 2k, c l = 100pf average of 256 events 4.5s
ltc2637 12 2637fb typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature dnl vs temperature reference output voltage vs temperature settling to 1lsb rising settling to 1lsb falling t a = 25c, unless otherwise noted. ltc2637-h12 (internal reference, v fs = 4.096v) code 0 inl (lsb) 1.0 0.5 0 C0.5 C1.0 1024 3072 2637 g08 4095 2048 v cc = 5v code 0 dnl (lsb) 1.0 0.5 0 C0.5 C1.0 1024 3072 2637 g09 4095 2048 v cc = 5v temperature (c) C50 inl (lsb) 1.0 0.5 0 C0.5 C1.0 C25 125 100 75 50 25 2637 g10 150 0 v cc = 5v inl (pos) inl (neg) temperature (c) C50 dnl (lsb) 1.0 0.5 0 C0.5 C1.0 C25 125 100 75 50 25 2637 g11 150 0 v cc = 5v dnl (pos) dnl (neg) temperature (c) C50 v ref (v) 2.068 2.058 2.048 2.038 2.028 C25 125 100 75 50 25 2637 g12 150 0 v cc = 5v scl 5v/div v out 1lsb/div 2s/div 2637 g13 9th clock of 3rd data byte 1/4 scale to 3/4 scale step v cc = 5v, v fs = 4.095v r l = 2k, c l = 100pf average of 256 events 4.1s scl 5v/div v out 1lsb/div 2s/div 2637 g14 9th clock of 3rd data byte 3/4 scale to 1/4 scale step v cc = 5v, v fs = 4.095v r l = 2k, c l = 100pf average of 256 events 5s
ltc2637 13 2637fb typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) integral nonlinearity (inl) differential nonlinearity (dnl) load regulation current limiting offset error vs temperature ltc2637-10 ltc2637-8 ltc2637 t a = 25c, unless otherwise noted. code 0 inl (lsb) 1.0 0.5 0 C0.5 C1.0 256 768 2637 g15 1023 512 v cc = 3v v fs = 2.5v internal ref. code 0 dnl (lsb) 1.0 0.5 0 C0.5 C1.0 256 768 2637 g16 1023 512 v cc = 3v v fs = 2.5v internal ref. code 0 inl (lsb) 0.50 0.25 0 C0.25 C0.50 64 192 2637 g17 255 128 v cc = 3v v fs = 2.5v internal ref. code 0 dnl (lsb) 0.50 0.25 0 C0.25 C0.50 64 192 2637 g18 255 128 v cc = 3v v fs = 2.5v internal ref. i out (ma) C30 $ v out (mv) 10 8 6 4 2 C6 C4 C2 0 C8 C10 C20 20 10 0 2637 g19 30 C10 v cc = 5v (ltc2637-h) v cc = 5v (ltc2637-l) v cc = 3v (ltc2637-l) internal ref. code = mid-scale i out (ma) C30 $ v out (v) 0.20 0.15 0.10 0.05 C0.15 C0.01 C0.05 0 C0.20 C20 20 10 0 2637 g20 30 C10 v cc = 5v (ltc2637-h) v cc = 5v (ltc2637-l) v cc = 3v (ltc2637-l) internal ref. code = mid-scale temperature (c) C50 offset error (mv) 3 2 1 0 C1 C2 C3 C25 125 100 75 50 25 2637 g21 150 0
ltc2637 14 2637fb typical performance characteristics large-signal response mid-scale glitch impulse power-on reset glitch headroom at rails vs output current exiting power-down to mid-scale power-on reset to mid-scale supply current vs logic voltage dac to dac crosstalk (dynamic) multiplying bandwidth ltc2637 t a = 25c, unless otherwise noted. 2s/div v out 0.5v/div 2637 g22 v fs = v cc = 5v 1/4 scale to 3/4 scale scl 5v/div v out 5mv/div 2s/div 2637 g23 9th clock of 3rd data byte ltc2637-h12 v cc = 5v, 3nv?s typ ltc2637-l12 v cc = 3v, 2.1nv?s typ 200s/div v out 5mv/div v cc 2v/div 2637 g24 ltc2637-l zero-scale i out (ma) 0 v out (v) 5.0 4.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.5 0 1789 6 5 4 3 2637 g25 10 2 5v sourcing 3v (ltc2637-l) sourcing 5v sinking 3v (ltc2637-l) sinking scl 5v/div v out 0.5v/div 5s/div 2637 g26 9th clock of 3rd data byte dacs a to g in power-down mode ltc2637h v cc = 5v internal ref logic voltage (v) 0 i cc (ma) 1.8 1.6 1.2 1.4 1.0 0.8 0.6 4 3 2 1 2637 g28 5 sweep sda, scl, between 0v and v cc v cc = 5v v cc = 3v (ltc2637-l) scl 5v/div v out 2mv/div 1 dac switch 0 to fs 2v/div 2s/div 2637 g29 9th clock of 3rd data byte ltc2637-h12 v cc = 5v, 3nv?s typ c ref = 0.1f 200s/div v cc 2v/div v out 0.5v/div 2637 g27 ltc2637-h ltc2637-l frequency (hz) db 2637 g30 2 0 C16 C14 C12 C10 C8 C6 C4 C2 C18 1k 100k 1m 10k v cc = 5v v ref(dc) = 2v v ref(ac) = 0.2v p-p code = full-scale
ltc2637 15 2637fb typical performance characteristics gain error vs reference input 0.1hz to 10hz voltage noise t a = 25c, unless otherwise noted. reference voltage (v) 1 gain error (%fsr) 1.0 0.8 0.6 0.4 C0.6 C0.8 C0.4 C0.2 0.2 0 C1.0 1.5 5 4.5 4 2637 g34 5.5 2 2.5 3 3.5 v cc = 5.5v gain error of 8 channels 1s/div 10v/div 2637 g35 v cc = 5v, v fs = 2.5v code = mid-scale internal ref. gain error vs. temperature noise voltage vs. frequency ltc2637 temperature (c) C50 gain error (%fsr) 1.0 0.5 0 C0.5 C1.0 C25 125 100 75 50 25 2637 g31 150 0 frequency (hz) 100 noise voltage (nv/ hz ) 500 400 300 200 100 0 1k 100k 2637 g32 1m 10k v cc = 5v code = mid-scale internal ref. ltc2637-h ltc2637-l
ltc2637 16 2637fb pin functions v cc (pin 1/pin 1): supply voltage input. 2.7v v cc 5.5v (ltc2637-l) or 4.5v v cc 5.5v (ltc2637-h). bypass to gnd with a 0.1f capacitor. v outa to v outh (pins 2C5, 10C13/pins 2C5, 12C15): dac analog voltage outputs. cao (pin 6/pin 7): chip address bit 0. tie this pin to v cc , gnd or leave it ? oating to select an i 2 c slave address for the part (see tables 1 and 2). scl (pin 7/pin 8): serial clock input pin. data is shifted into the sda pin at the rising edges of the clock. this high impedance pin requires a pull-up resistor or current source to v cc . sda (pin 8/pin 9): serial data bidirectional pin. data is shifted into the sda pin and acknowledged by the sda pin. this pin is high impedance while data is shifted in. open drain n-channel output during acknowledgment. sda requires a pull-up resistor or current source to v cc . ref (pin 9/pin 11): reference voltage input or output. when external reference mode is selected, ref is an input (1v v ref v cc ) where the voltage supplied sets the full-scale dac output voltage. when internal reference is selected, the 10ppm/c 1.25v (ltc2637-l) or 2.048v (ltc2637-h) internal reference (half full-scale) is available at the pin. this output may be bypassed to gnd with up to 10f, and must be buffered when driving external dc load current. gnd (pin 14/pin 16): ground. ca2 (pin 6, msop only): chip address bit 2. tie this pin to v cc , gnd or leave it ? oating to select an i 2 c slave ad- dress for the part (see table 1). ca1 (pin 10, msop only): chip address bit 1. tie this pin to v cc , gnd or leave it ? oating to select an i 2 c slave address for the part (see table 1). exposed pad (pin 15, dfn only): ground. must be soldered to pcb ground. (dfn/msop)
ltc2637 17 2637fb block diagram test circuits 2637 bd gnd v outa v outb v outc v outd cao (ca1) (ca2) ref v cc v outh v outg v outf v oute scl internal reference switch dac a decode power-on reset v ref v ref v ref v ref v ref v ref v ref dac b dac c dac d dac h dac g dac f dac e register i 2 c address decode ( ) msop package only register register register register register register register register register register register register register register register sda i 2 c interface 2637 tc01 100 ca n v ih(ca n ) /v il(ca n ) test circuit 1 2637 tc01b ca n r inh /r inl /r inf v dd gnd test circuit 2
ltc2637 18 2637fb timing diagram figure 2. typical ltc2637 write transaction ack ack 123456789123456789123456789123456789 2637 f02 ack start a6 a5 a4 a3 slave address a2 a1 a0 w scl c2 c3 c1 c0 a3 a2 a1 a0 xxxx ack 1st data byte 2nd data byte 3rd data byte figure 1. i 2 c timing t f sda scl ssrs p t f t r t buf t r t low t hd(sta) t su(sta) t su(sto) t hd(dat) all voltage levels refer to v ih(min) and v il(max) levels t high t su(dat) t hd(sta) t sp 2637 f01
ltc2637 19 2637fb operation the ltc2637 is a family of octal voltage output dacs in 14-lead dfn and 16-lead msop packages. each dac can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. eighteen combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zero-scale, mid-scale in internal reference mode, or mid-scale in external reference mode), and full- scale voltage (2.5v or 4.096v) are available. the ltc2637 is controlled using a 2-wire i 2 c interface. power-on reset the ltc2637-hz/ ltc2637-lz clear the output to zero-scale when power is ? rst applied, making system initialization consistent and repeatable. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2637 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mv above zero- scale during power on. in general, the glitch amplitude decreases as the power supply ramp time is increased. see power-on reset glitch in the typical performance characteristics section. the ltc2637-hmi/ltc2637-hmx/ltc2637-lmi/ ltc2637-lmx provide an alternative reset, setting the output to mid-scale when power is ? rst applied. the ltc2637-lmi and ltc2637-hmi power up in internal reference mode, with the output set to a mid-scale volt- age of 1.25v and 2.048v, respectively. the ltc2637-lmx and ltc2637-hmx power-up in external reference mode, with the output set to mid-scale of the external reference. default reference mode selection is described in the refer- ence modes section. power supply sequencing the voltage at ref (pin 9, dfn; pin 11, msop) must be kept within the range C0.3v v ref v cc + 0.3v (see absolute maximum ratings). particular care should be taken to observe these limits during power supply turn- on and turn-off sequences, when the voltage at v cc is in transition. transfer function the digital-to-analog transfer function is: v out(ideal) = k 2 n ? ? ? ? ? ? v ref where k is the decimal equivalent of the binary dac input code, n is the resolution, and v ref is either 2.5v (ltc2637-lmi/ltc2637-lmx/ltc2637-lz) or 4.096v (ltc2637-hmi/ltc2637-hmx/ltc2637-hz) when in internal reference mode, and the voltage at ref when in external reference mode. i 2 c serial interface the ltc2637 communicates with a host using the stan- dard 2-wire i 2 c interface. the timing diagrams (figures 1 and 2) show the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the value of these pull-up resistors is dependent on the power supply and can be obtained from the i 2 c speci? cations. for an i 2 c bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pf. the ltc2637 is a receive-only (slave) device. the master can write to the ltc2637. the ltc2637 will not acknowl- edge (nak) a read request from the master. start (s) and stop (p) conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a communica- tion to a slave device by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. when the master has ? nished communicating with the slave, it issues a stop condition. a stop condition is generated by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device.
ltc2637 20 2637fb operation acknowledge the acknowledge (ack) signal is used for handshaking between the master and the slave. an ack (active low) generated by the slave lets the master know that the lat- est byte of information was properly received. the ack related clock pulse is generated by the master. the master releases the sda line (high) during the ack clock pulse. the slave-receiver must pull down the sda bus line dur- ing the ack clock pulse so that it remains a stable low during the high period of this clock pulse. the ltc2637 responds to a write by a master in this manner but does not acknowledge a read operation; in that case, sda is retained high during the period of the ack clock pulse. chip address the state of pins ca0, ca1 and ca2 (ca1 and ca2 are only available on the msop package) determines the slave address of the part. these pins can each be set to any one of three states: v cc , gnd or ? oat. this results in 27 (msop package) or 3 (dfn package) selectable addresses for the part. the slave address assignments are shown in tables 1 and 2. in addition to the address selected by the address pins, the part also responds to a global address. this address allows a common write to all ltc2637 parts to be ac- complished using one 3-byte write transaction on the i 2 c bus. the global address, listed at the end of tables 1 and 2, is a 7-bit hardwired address not selectable by ca0, ca1 or ca2. if another global address is required, please consult the factory. the maximum capacitive load allowed on the address pins (ca0, ca1 and ca2) is 10pf, as these pins are driven during address detection to determine if they are ? oating. table 1. slave address map (msop package) ca2 ca1 ca0 a6 a5 a4 a3 a2 a1 a0 gndgndgnd0010000 gndgndfloat0010001 gnd gnd v cc 0010010 gndfloatgnd0010011 gndfloatfloat0100000 gnd float v cc 0100001 gnd v cc gnd0100010 gnd v cc float0100011 gnd v cc v cc 0110000 floatgndgnd0110001 floatgndfloat0110010 float gnd v cc 0110011 floatfloatgnd1000000 floatfloatfloat1000001 float float v cc 1000010 float v cc gnd1000011 float v cc float1010000 float v cc v cc 1010001 v cc gndgnd1010010 v cc gndfloat1010011 v cc gnd v cc 1100000 v cc floatgnd1100001 v cc floatfloat1100010 v cc float v cc 1100011 v cc v cc gnd1110000 v cc v cc float1110001 v cc v cc v cc 1110010 global address 1110011 table 2. slave address map (dfn package) ca0 a6a5a4a3a2a1a0 gnd 0010000 float 0010001 v cc 0010010 global address 1 1 1 0 0 1 1
ltc2637 21 2637fb operation write word protocol the master initiates communication with the ltc2637 with a start condition and a 7-bit slave address followed by the write bit ( w ) = 0. the ltc2637 acknowledges by pulling the sda pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by ca0, ca1 or ca2) or the global address. the master then transmits three bytes of data. the ltc2637 acknowledges each byte of data by pulling the sda line low at the 9th clock of each data byte transmission. after receiving three complete bytes of data, the ltc2637 executes the command speci? ed in the 24-bit input word. if more than three data bytes are transmitted after a valid 7-bit slave address, the ltc2637 does not acknowledge the extra bytes of data (sda is high during the 9th clock). the format of the three data bytes is shown in figure 3. the ? rst byte of the input word consists of the 4-bit command, followed by the 4-bit dac address. the next two bytes contain the 16-bit data word, which consists of the 12-, 10- or 8-bit input code, msb to lsb, followed by 4, 6 or 8 dont-care bits (ltc2637-12, ltc2637-10 and ltc2637-8, respectively). a typical ltc2637 write transaction is shown in figure 4. the command bit assignments (c3-c0) and address (a3- a0) assignments are shown in tables 3 and 4. the ? rst four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register. in an update operation, the data word is copied from the input register to the dac register. once copied into the dac register, the data word becomes the active 12-, 10-, or 8-bit input code, and is converted to an analog voltage at the dac output. write to and update combines the ? rst two commands. the update operation also powers up the dac if it had been in power-down mode. the data path and registers are shown in the block diagram. table 3. command codes command* c3 c2 c1 c0 0000w rite to input register n 0001u pdate (power up) dac register n 0010w rite to input register n, update (power up) all 0011w rite to and update (power up) dac register n 0100power down n 0101power down c hip (all dacs and reference) 0110s elect internal reference (power up reference) 0111s elect external reference (power down internal reference) 1111no o peration *command codes not shown are reserved and should not be used. table 4. address codes address (n)* a3 a2 a1 a0 0000dac a 0001dac b 0010dac c 0011dac d 0100dac e 0101dac f 0110dac g 0111dac h 1111all dacs *address codes not shown are reserved and should not be used. reference modes for applications where an accurate external reference is either not available, or not desirable due to limited space, the ltc2637 has a user-selectable, integrated reference. the integrated reference voltage is internally ampli? ed by 2x to provide the full-scale dac output voltage range.
ltc2637 22 2637fb operation figure 3. command and data input format c3 1st data byte input word (ltc2637-12) write word protocol for ltc2637 c2 c1 c0 a3 a2 a1 a1 d9 d10 d11 s w ack slave address 1st data byte d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x ack 2nd data byte ack 3rd data byte ack p 2637 f03 2nd data byte input word 3rd data byte c3 1st data byte input word (ltc2637-10) c2 c1 c0 a3 a2 a1 a0 d7 d8 d9 d6 d5 d4 d3 d2 d1 d0 xxxxx x 2nd data byte 3rd data byte c3 1st data byte input word (ltc2637-8) c2 c1 c0 a3 a2 a1 a0 d5 d6 d7 d4 d3 d2 d1 d0 x x xxxxx x 2nd data byte 3rd data byte the ltc2637-lmi/ ltc2637-lmx/ ltc2637-lz provides a full-scale output of 2.5v. the ltc2637-hmi/ ltc2637- hmx/ ltc2637-hz provides a full-scale output of 4.096v. the internal reference can be useful in applications where the supply voltage is poorly regulated. internal reference mode can be selected by using command 0110b, and is the power-on default for ltc2637-hz/ ltc2637-lz, as well as for ltc2637-hmi/ ltc2637-lmi. the 10ppm/c, 1.25v (ltc2637-lmi/ ltc2637-lmx/ ltc2637-lz) or 2.048v (ltc2637-hmi/ ltc2637-hmx/ ltc2637-hz) internal reference is available at the ref pin. adding bypass capacitance to the ref pin will improve noise performance; and up to 10f can be driven without oscillation. the ref output must be buffered when driving an external dc load current. alternatively, the dac can operate in external reference mode using command 0111b. in this mode, an input voltage supplied externally to the ref pin provides the reference (1v v ref v cc ) and the supply current is reduced. the external reference voltage supplied sets the full-scale dac output voltage. external reference mode is the power-on default for ltc2637-hmx/ ltc2637-lmx. the reference mode of ltc2637-hz/ ltc2637-lz/ ltc2637- hmi/ ltc2637-lmi (internal reference power-on default), can be changed by software command after power up. the same is true for ltc2637-hmx/ ltc2637-lmx (external reference power-on default). power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight dac outputs are needed. when in power-down, the buffer ampli? ers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. the dac outputs are put into a high-impedance state, and the output pins are passively pulled to ground through in- dividual 200k resistors. input and dac register contents are not disturbed during power down. any dac channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate dac address, (n). the supply current is reduced approximately 10% for each dac powered down. the integrated reference is automatically powered down when external reference is selected using
ltc2637 23 2637fb operation command 0111b. in addition, all the dac channels and the integrated reference together can be put into power- down mode using power down chip command 0101b. when the integrated reference and all dac channels are in power-down mode, the ref pin becomes high imped- ance (typically > 1g). for all power-down commands the 16-bit data word is ignored. normal operation resumes after executing any command that includes a dac update, (as shown in table 1). the selected dac is powered up as its voltage output is up- dated. when a dac which is in a powered-down state is powered up and updated, normal settling is delayed. if less than eight dacs are in a powered-down state prior to the update command, the power-up delay time is 10s. however, if all eight dacs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the dac ampli? ers and reference buffers. in this case, the power up delay time is 12s. the power-up of the integrated reference depends on the command that pow- ered it down. if the reference is powered down using the select external reference command (0111b), then it can only be powered back up using select internal reference command (0110b). however, if the reference was powered down using power down chip command (0101b), then in addition to select internal reference command (0110b), any command that powers up the dacs will also power up the integrated reference. voltage output the ltc2637s dac output integrated rail-to-rail ampli? ers have guaranteed load regulation when sourcing or sinking up to 10ma at 5v, and 5ma at 3v. load regulation is a measure of the ampli? ers ability to maintain the rated voltage accuracy over a wide range of load current. the measured change in output voltage per change in forced load current is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the ampli? ers dc output impedance is 0.1 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50 typical channel resistance of the output devices (e.g., when sinking 1ma, the minimum output voltage is 50 ? 1ma, or 50mv). see the graph headroom at rails vs. output current in the typical performance charac- teristics section. the ampli? er is stable driving capacitive loads of up to 500pf. rail-to-rail output considerations in any rail-to-rail voltage output device, the output is lim- ited to voltages within the supply range. since the analog output of the dac cannot go below ground, it may limit for the lowest codes as shown in figure 5b. similarly, limiting can occur near full scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc , as shown in figure 5c. no full-scale limiting can occur if v ref is less than v cc Cfse. offset and linearity are de? ned and tested over the region of the dac transfer function where no output limiting can occur. board layout the pc board should have separate areas for the analog and digital sections of the circuit. a single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. this keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the
ltc2637 24 2637fb analog section of the ground plane. the resistance from the ltc2637 gnd pin to the ground plane should be as low as possible. resistance here will add directly to the effective dc output impedance of the device (typically 0.1). note that the ltc2637 is no more susceptible to this effect than any other parts of this type; on the con- trary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. another technique for minimizing errors is to use a sepa- rate power ground return trace on another board layer. the trace should run between the point where the power supply is connected to the board and the dac ground pin. thus the dac ground pin becomes the common point for analog ground, digital ground, and power ground. when the ltc2637 is sinking large currents, this current ? ows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. it is sometimes necessary to interrupt the ground plane to con? ne digital ground currents to the digital portion of the plane. when doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. operation a6 a5 a4 a3 a2 a1 a0 w c3 c3 ack slave address ack ack ack c2 c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 xxxx a6 start stop full-scale voltage zero-scale voltage sda scl x = dont care v out a5 a4 a3 a2 a1 a0 c2 c1 c0 a3 a2 a1 a0 8912345 67 12345 67 89 12345 67 89123456789 command/address ms data ls data 2637 f04 figure 4. typical ltc2637 input waveformprogramming dac output for full-scale figure 5. effects of rail-to-rail operation on a dac transfer curve (shown for 12 bits). (a) overall transfer function (b) effect of negative offset for codes near zero (c) effect of positive full-scale error for codes near full-scale 2637 f04 input code (b) output voltage negative offset 0v 0v 2,048 0 4,095 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positive fse
ltc2637 25 2637fb typical application 2637 ta02 ltc2637ms-lmi12 dac a dac b dac c dac d dac h dac g dac f dac e ref sda scl ca0 ca1 ca2 v cc 0.1f 0.1f m9 m3 m1 p1 p3 p9 8 9 10 1 2 3 lt1991 v cc v ee ref out 6 v out = 5v 0.1f 0.1f 5 4 7 C15v 15v 5v 1 15 14 13 12 10 7 6 gnd 16 11 2 3 4 5 8 9 C + 0.1f 0.1f 15v C15v 1/2 lt1469 dac a 8 4 1 30k lt1634-1.25 lt1634-1.25 C15v i 2 c bus outa 60 61 15 64 63 62 59 2 58 + C outb r fba r vosa 19 gnd i out1a i out2a 3 2 30k C15v dac b v dd r ofsa r in1 r com1 refa dac d + C outd dac c + C outc C + 1/2 lt1469 0.1f 0.1f 15v C15v 8 4 5 6 7 0.1f 5v 30k C15v 30k C15v ltc2755 ltc6240 + C lt1634-1.25 lt1634-1.25 ltc2637 dacs adjust ltc2755-16 offsets, ampli? ed with lt1991 pga to 5v
ltc2637 26 2637fb package description 3.00 p 0.10 (2 sides) 4.00 p 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom viewexposed pad 1.70 p 0.10 0.75 p 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1.70 p 0.05 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 s 45 o chamfer 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 p 0.05 0.70 p 0.05 3.60 p 0.05 package outline 0.25 p 0.05 0.25 p 0.05 0.50 bsc 3.30 p 0.05 3.30 p 0.10 0.50 bsc de package 14-lead (4mm 3mm) plastic dfn (reference ltc dwg # 05-08-1708 rev b) ms package 16-lead (4mm 5mm) plastic msop (reference ltc dwg # 05-08-1669 rev ?) msop (ms16) 1107 rev ? 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 12345678 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 o C 6 o typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 0.50 (.0197) bsc 4.039 p 0.102 (.159 p .004) (note 3) 0.1016 p 0.0508 (.004 p .002) 3.00 p 0.102 (.118 p .004) (note 4) 0.280 p 0.076 (.011 p .003) ref 4.90 p 0.152 (.193 p .006)
ltc2637 27 2637fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 10/09 update ltc2637-12 maximum limits 5, 6, 8 b 06/10 added details to note 3 revised typical application circuit added typical application drawing and revised related parts 10 25 28
ltc2637 28 2637fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0610 rev b ? printed in usa part number description comments ltc2636 octal 12-/10-/8-bit, spi v out dacs with 10ppm/c reference 125a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, 14-lead 4mm 3mm dfn and 16-lead msop packages ltc1660/ltc1665 octal 10/8-bit v out dacs in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc2605/ltc2615/ ltc2625 octal 16-/14-/12-bit v out dacs with i 2 c interface 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output, i 2 c interface ltc2600/ltc2610/ ltc2620 octal 16-/14-/12-bit v out dacs in 16-lead narrow ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2656/ltc2657 octal 16-/12 bit, spi/i 2 c v out dacs with 10ppm/c max reference 4lsb inl max at 16-bits and 2mv offset error, rail-to-rail output, 20-lead 4mm 5mm qfn and 16-lead tssop packages ltc2654/ltc2655 quad 16-/12 bit, spi/i 2 c v out dacs with 10ppm/c max reference 4lsb inl max at 16-bits and 2mv offset error, rail-to-rail output, 20-lead 4mm 4mm qfn and 16-lead narrow ssop packages ltc2634/ltc2635 quad 12-/10-/8-bit spi/i 2 c v out dacs with 10ppm/c reference 2.5 lsb inl, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, 16-pin 3mm 3mm qfn and 10-lead msop packages ltc2630/ltc2632 single 12-/10-/8-bit, spi/ i 2 c v out dacs with 10ppm/c reference 180a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, rail-to-rail output, in sc70 (ltc2630)/ thinsot ? (ltc2631) ltc2640 single 12-/10-/8-bit, spi v out dacs with 10ppm/c reference 180a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, in thinsot ampli? ers lt1991 precision, 100a gain selectable ampli? er gain accuracy of 0.04%, gains from C13 to 14, 100a precision op-amp lt1469 dual 90mhz, 22v/s 16-bit accurate operational ampli? er 90mhz gain bandwidth, 125v offset, 900ns , 22v/s slew rate precision op-amp related parts typical application ltc2637 dacs adjust ltc2755-16 offsets, ampli? ed with lt1991 pga to 5v 2637 ta03 ltc2637ms-lmi12 dac a dac b dac c dac d dac h dac g dac f dac e ref sda scl ca0 ca1 ca2 v cc 0.1f 0.1f m9 m3 m1 p1 p3 p9 8 9 10 1 2 3 lt1991 v cc v ee ref out 6 v out = 5v 0.1f 0.1f 5 4 7 C15v 15v 5v 1 15 14 13 12 10 7 6 gnd 16 11 2 3 4 5 8 9 C + 0.1f 0.1f 15v C15v 1/2 lt1469 dac a 8 4 1 30k lt1634-1.25 lt1634-1.25 C15v i 2 c bus outa 60 61 15 64 63 62 59 2 58 + C outb r fba r vosa 19 gnd i out1a i out2a 3 2 30k C15v dac b v dd r ofsa r in1 r com1 refa dac d + C outd dac c + C outc C + 1/2 lt1469 0.1f 0.1f 15v C15v 8 4 5 6 7 0.1f 5v 30k C15v 30k C15v ltc2755 ltc6240 + C lt1634-1.25 lt1634-1.25

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